
This example shows some combinations of event types
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1. time based match
2. input rising edge
3. match and input low

The SCT is configured in unified mode (one 32-bit timer).


Notes:

the third event will happen only when both conditions are satisfied, so the last transition back to state U_ENTRY will depend on the
relatime timing between the CPU generated signal and the counter match 'count' condition.
Modifying the CPU loop will change the amount of time for which the SCT will be kept in the Test3__state, 
until the 'AND' condition is satisfied.

For convenience, the same count value is also used to generate a reference signal (TIMING_REF toggling) used to determine
when the counter reaches the 'count' value, to analyze the diagrams more easily.

There is also another event which is in the ALWAYS pseudo state and used to limit the timer to count upto a maximum value 'maxcount'
This to avoid waiting for the counter to roll-over in case we are in Test3_state and the TEST_IN input is not low at the moment
the timer match 'count' happens.
